The present invention is related to integrated circuit memories, and, more particularly, to a clock distribution tree for minimizing data skew between data drivers and associated input buffers in the memory.
Capture windows for inputs and outputs on today's high speed memories are becoming smaller. Input set up times (tS) and hold times (tH) are reduced as clock frequencies increase. Clock and signal skew are becoming larger as chip sizes increase. Because of these two trends, higher speed systems and larger chip size or RAM macro size, the actual valid time is being reduced for inputs and outputs to RAM circuit blocks.
Typical clock distribution trees 100 are shown in FIGS. 1(a)-1(d). There are many different ways to distribute or route a clock or control signal around a silicon integrated circuit. These many different ways of routing have different skew values or time differences between the closest (fastest) location and the furthest (slowest) location. The signal propagation time or skew depends on the length that the line needs to travel, the width of the line, the space of the line, the number of tree branches if any, and the transistor load on the line. FIG. 1(a) shows a clock distribution tree wherein inverters I30 and I31 are used to drive a first portion of a clock bus, and inverters I34 and I35 are used to drive a second portion of a clock bus. In turn, inverters I30 and I35 are driven by inverters I36 and I37. FIG. 1(b) shows a clock distribution tree wherein inverters I51 and I52 are used to drive the entire clock bus. FIG. 1(c) shows a clock distribution tree wherein a single inverter I41 is used to drive a first portion of a clock bus, and another single inverter I40 is used to drive a second portion of a clock bus. In turn, inverters I41 and I40 are driven by inverter I39. FIG. 1(d) shows a single inverter I56 for driving a first portion of a clock bus, a single inverter I55 for driving a second portion of a clock bus, a single inverter I54 for driving a third portion of a clock bus, and a single inverter I53 for driving a fourth portion of a clock bus. In turn, inverters I56 and I55 are driven by inverter I46. Inverters I53 and I54 are driven by inverter I45. Inverters I45 and I46 are finally driven by inverters I57 and I44.
A clock distribution tree is shown for a portion of an integrated circuit memory 200 in FIG. 2. Integrated circuit memory 200 includes input buffers 202 designated 0 through 7. Each input buffer has a data input, a data output (not shown), and a clock input. Integrated circuit memory 200 also includes data drivers 204 designated 0 through 7, corresponding to each of the input buffers. Only the clock input and the data output of the data drivers 204 is shown in FIG. 2. The data drivers 204 are clocked by a first clock distribution tree originating from signal ACLK including inverters I53-I57 and I44-I46. Inverter I56 clocks data drivers 6 and 7, inverter I55 clocks data drivers 4 and 5, inverter I54 clocks data drivers 2 and 3, and inverter I53 clocks data drivers 0 and 1. In turn, inverters I55 and I56 are driven by inverter I46, and inverters I53 and I54 are driven by inverter I45. Inverters I45 and I46 are driven by inverters I44 and I57. The widths and spacings of the ACLK signal routing before and after these clock tree inverters are noted as Iμ, Jμ, Gμ, . . . Eμ, indicating I, J, G and E microns. For example, the width of the line running from inverter I53 to data driver 0 is Iμ. The clock tree is balanced and symmetrical in that the line width from inverter I54 to data driver 3 is also Iμ. The spacing of each of these lines to adjacent lines is also the same as Jμ. The input buffers 202 are clocked by a second clock distribution tree coming from signal BCLK including inverters I30-I31 and I34-I37. Inverters I30 and I31 clocks data drivers 4-7, and inverters I34 and I35 clocks data drivers 0-3. In turn, inverters I30 and I35 are driven by inverters I36 and I37. The widths and spacings of the BCLK signal tree are noted by the labels Aμ, Bμ, Cμ, and Dμ, indicating A, B, C, and D microns.
It is important to note in FIG. 2 that the two clock distribution trees are not matched. The topology of the clock distribution trees is different for clocking the input buffers 202 and the data drivers 204. Further, the widths and spacings associated with the various clock busses and clock bus segments is also unmatched. This leads to clock and data skew and loss of performance.
On prior art circuits even if good engineering practices are used, the valid data window can be reduced depending on the particular clock tree used. The block diagram of FIG. 2 shows the clock tree used to control input buffers 202 designated 0 through 7 on an embedded RAM BLOCK circuit 206. The latching of input buffers 1 and 2 are fastest and of the input buffers 4 and 7 are the slowest. The low skew clock tree chosen to provide data for these input buffers offers almost zero skew. In other words, the ACLK tree distribution design contains almost no skew or timing difference from enabling data drivers 204 in all eight locations, 0 through 7. So even though this is a better design to reduce skew, it is inferior in maximizing the valid data window for these buffers. Buffers 1 and 2 will have reduced set up times and buffers 4 and 7 will have reduced hold times.
What is desired, therefore, is a clock distribution tree and method that maximizes valid times for inputs and outputs to RAM circuit blocks in an integrated circuit memory.